The present invention relates to a manufacturing method for a metal-oxide semiconductor device, wherein an actuation of a parasite bipolar transistor is prevented without any increase of on-resistance or sacrifice of turn-off capacity.
The metal-oxide semiconductor devices include power MOSFETs, which utilize only one type of charge carriers, and insulated gate bipolar transistors ("IGBT") (also called "IGT" or "COMFET"), which utilize both electrons and holes as charge carriers.
FIG. 2 is a sectional view showing the structure of a prior art power MOSFET having an n-type channel element. The formation of such a device is described in U.S. patent application Ser. No. 07/316,474 filed on Feb. 27, 1989 now U.S. Pat. No. 4,914,047 and incorporated herein by reference. The initial step in the manufacture of such a power MOSFET is epitaxially forming an n.sup.- layer 1 on a semiconductor substrate functioning as a drain, namely the n.sup.+ layer 2. Next, a p.sup.+ layer 3 is formed by diffusion, which is embedded in the n.sup.- layer 1. A gate insulating film 41 is next formed, followed by forming of a gate electrode 5 over the gate insulating film 41. Subsequently, the gate electrode 5 is windowed through photolithography. Then, a p-type base layer 6 is formed by diffusion, with the windowed gate electrode 5 functioning as a mask. Next, a p.sup.+ low-resistance layer 7 is similarly formed in the p-layer 6 through photolithography and diffusion. An n.sup.+ layer 8, functioning as a source, is then formed with the gate electrode 5 again working as a part of a mask. The top surface, of which the gate electrode 5 forms a portion, is coated with an insulating film 42 and windowed to facilitate connection between the source layer 8 and a source electrode 11, which is next formed. Finally, a drain electrode 12 is formed to contact the n.sup.+ layer 2.
In the prior art power MOSFET, when a positive voltage is applied to the gate electrode 5, relative to the source electrode 11, an n-channel 9 is formed on the surface of the p-type base layer 6, directly under the gate insulating film 41. In this condition, electrons are injected from the source layer 8 to the drain layer, which consists of the high-resistance layer 1 and the lower resistance layer 2, via an induced n-channel 9. Consequently, the gate electrode 5 is kept at equipotential to the source electrode. If a negative voltage is subsequently applied to the gate electrode 5, relative to the source electrode 11, or negative-biased, no conducting channel exists between the source layer and the drain layer. By changing the biasing between the source layer and the drain layer, as described above, the prior art power MOSFET can be used as a switching element.
FIG. 3 represents a prior art IGBT, which can be produced through a process similar to the process for manufacturing power MOSFETs. Such a process is described in U.S. patent application Ser. No. 07/316,462 filed Feb. 27, 1989 and incorporated herein by reference. Since the drain layer 10 of the IGBT is a p.sup.+ type material, holes are injected from the p.sup.+ drain layer 10 to the n.sup.- layer 1 via the n.sup.+ -buffer layer 2, simultaneously with the injection of electrons from the source layer 8 to the p.sup.+ layer 10 via the n.sup.- layer and the n.sup.+ buffer layer 2. Consequently, the n.sup.- layer 1 causes a conductivity modulation, thereby reducing its resistance.
When a prior art MOSFET shown in FIG. 5 is turned off while connected to an inductive load, a depletion layer 22 quickly forms on both sides of a p-n junction 21. When the depletion layer is formed, a hole-drift current 23 is generated, which current flows from the depletion region to the p.sup.+ low-resistance layer 7, via the p base layer 6 under the n.sup.+ source layer 8. Since the source electrode 11 electrically connects the surface of the p layer 6 and the n.sup.+ source layer 8, a potential difference between the two layers is produced as a result of the hole current 23 and a base resistance R.sub.b. When the potential difference exceeds a built-in voltage between the base layer 6 and the source layer 8, electrons are injected from the source layer 8 to the n.sup.- layer 1, thereby actuating an NPN parasitic transistor consisting of the n.sup.- source layer 8, the p base layer 6, and n.sup.- layer 1. As a result, current flows through the parasitic transistor, resulting in a breakdown of the transistor element.
It is well-known that the p.sup.+ diffusion layer 3 of FIG. 2 is formed to minimize the hole current 23 shown in FIG. 5, thereby preventing the breakdown of the element. Similarly, the p.sup.+ low resistance layer 7 is formed to prevent the breakdown of the element. The p.sup.+ layer 7 minimizes the base resistance R.sub.b, thereby preventing the parasitic transistor from turning on. Despite the above-described structural elements, unwanted actuation of the parasitic transistor, in a power MOSFET connected to an inductive load, is not adequately curtailed.
In the case of an IGBT shown in FIG. 3, the IGBT connected to an inductive load may breakdown, when turned off, due to the actuation of the parasitic transistor consisting of the n.sup.+ source layer 8, the p base layer 6, and the n.sup.- layer 1. Furthermore, the hole current 23 shown in FIG. 5 flows in the IGBT even in a normal on-state. Consequently, the actuation of the parasitic transistor may occur in the IGBT even when it is in the normal on-state, or when the IGBT is not connected to an inductive load at the time of turn-off. As in the prior art power MOSFET, the p.sup.+ diffusion layer 3 and the p.sup.+ low resistance layer 7 are formed in the prior art IGBT to prevent the actuation of the parasitic transistor. Once again, the actuation of the parasitic transistor is not adequately curtailed.
The problems of the prior art are further explained in conjunction with FIG. 4, which represents an inverter circuit for driving a motor 55. The inverter circuit consists of four MOSFETs 51 to 54 of the type of MOSFET shown in FIG. 2. Diodes 31 to 34, each of which is formed of a p region and an n.sup.- layer, are incorporated in the MOSFET's 51 to 54, respectively. The above-mentioned p region consists of the p.sup.+ layer 3, the p layer 6, and the p.sup.+ layer 7, all as shown in FIG. 2. The n.sup.- layer of the diode is the layer 1 in FIG. 2.
From an initial state, in which the motor 55 is driven with the MOSFET's 52 and 53 on, the MOSFET 52 is subsequently turned off, and a load current is commutated to the diode 31 of the MOSFET 51. Next, when the MOSFET 52 is turned on, a reverse-recovery current of the diode 31 flows in addition to the load current. During the reverse-recovery time of the diode 31, a parasitic bipolar transistor of the MOSFET 52, which consists of the n.sup.+ source layer 8, the p base layer 6, and the n.sup.- layer 1, is turned on. Consequently, a breakdown of the MOSFET occurs. The parasitic bipolar transistor is turned on due to a large reverse-recovery current of the diode 31, which results in a sudden rise of the voltage into the avalanche region, and also due to a current generated by a high dv/dt.
Several plausible methods of preventing an actuation of the parasitic bipolar transistor exist. One method is to prevent the commutation current from flowing to the built-in diode by incorporating an external free-wheeling diode and a Schottky barrier diode. Another method is to reduce the di/dt and the dv/dt by increasing an external gate resistance. Yet another method to enhance the breakdown capacity by reducing the reverse-recovery current and the reverse-recovery time of the built-in diode.
The first two of the above-described methods involve increased number of components and, hence, increased cost. The last method is also problematic. If a lifetime-reducing agent, platinum for example, is introduced to reduce the reverse recovery time, an on-resistance increases. Consequently, power loss is increased, which is not desirable.
Accordingly, it is an object of the present invention to eliminate the above-described problems in the prior art. This object is attained by providing a manufacturing method for a metal-oxide semiconductor device in which the reverse-recovery time of a built-in diode is reduced, without an increase in the on-resistance, to prevent an actuation of the parasitic bipolar transistor, while maintaining a powerful turn-off capacity.